1. Field of the Invention
The present invention relates generally to signal converters.
2. Description of the Related Art
Pipelined analog-to-digital converters (ADCs) are capable of achieving impressive resolution and performance (e.g., 10 bit quantization and 80 dB spurious free dynamic range) at high sample rates (e.g., 200 megasamples per second). Accordingly, they are useful in a wide range of demanding converter applications (e.g., charge-coupled device (CCD) imaging, ultrasonic medical imaging, base station processing, digital receivers, digital video, cable modems, digital subscriber line (DSL) systems, and Ethernet systems).
In an initial converter stage of an exemplary pipelined ADC structure, a first sample of an analog input signal is initially provided to that stage's converter which quantizes the analog sample to a corresponding n digital bits. An associated digital-to-analog converter (DAC) in the initial stage converts the n digital bits to a corresponding analog signal which is subtracted from the first analog sample to provide a “residue signal”.
To complete the conversion of the first analog sample, this residue signal is converted to one or more corresponding digital codes in one or more downstream converter stages. To enhance conversion accuracy in the first succeeding downstream converter stage, the residue signal of the initial stage is “gained up” in an amplifier so that the analog window presented to the succeeding stage substantially matches the analog window presented to the initial stage.
The gained-up residue is then passed to the succeeding downstream stage for conversion to a corresponding m digital bits in a manner similar to that described above in the initial converter stage wherein m may or may not equal n. Because the residue is “multiplied”, the structure that provides the gained-up residue is typically referred to as a multiplying DAC or, equivalently, an MDAC.
This conversion process continues in succeeding converter stages until there is no further residue to be converted. It is important to understand that the processing of the first sample in each converter stage takes place while the stage immediately upstream is processing a succeeding second sample of the analog input signal. If there are N converter stages, therefore, it will take N clock cycles to complete the conversion of the first analog sample in the “pipelined” structure.
The converted bits from each stage are appropriately delayed in digital registers so that they are all aligned when the last bits become available. To enhance the conversion accuracy, the converter stages are often configured to produce redundant bits and all bits are processed with a digital error correction technique to derive the final corresponding digital code.
The residue signals of pipelined converters are often generated in switched-capacitor. MDACs in which one or more capacitors in a succeeding converter stage are switched to sample (acquire charge from) the residue signal of the preceding stage in a first portion of a system's clock period. In the latter portion of this clock period, one or more capacitors are switched to alter this residue signal in accordance with the quantization decision of the succeeding stage.
In particular, the quantization decision is used to select an appropriate one of predetermined reference signals which is then applied to at least one of the capacitors to transfer at least a portion of the previously-acquired charge to another of the capacitors. Generally, at least one capacitor is arranged about a high gain amplifier and the capacitors are sized and arranged to provide the multiplying gain referred to above.
It is apparent that any error in the value of the predetermined reference signals is directly transferred into error in the gained-up residue signal and thus the accuracy of the conversion process is degraded. Accordingly, the generation of the predetermined reference signals is critical to the performance of the converter system.